Title: Controlling Lattice Disorder and Charge Flux in Atomically Thin Semiconductors
Abstract: Continued innovation in ubiquitous consumer electronics depends on breakthroughs in both materials synthesis and device architectures. Recently, a new class of layered semiconductors has shown promises for various electronic applications. In particular, single layer transition metal dichalcogenides (e.g. MoS2) present a host of attractive features such as high electrical conductivity, tunable band-gap, and strong light-matter interaction. Furthermore, atomically thin layers can stacked in arbitrary permutations to achieve van der Waals heterojunction devices. However, new challenges accompany new opportunities. Not only ‘all-surface’ nature of these two-dimensional (2D) materials can be strongly affected by the environment, the present growth strategies also produce polycrystalline films with significant lattice disorder.
In this presentation, I will first discuss the role of energetic disorder from the environment in charge transport in single layer MoS2 and van der Waals heterojunction devices. The stoichiometry of MoS2 grown by chemical vapor deposition is controlled to enhance device performance. Furthermore, point defects can migrate within single layers under the influence of an electric field. This unique control over 2D lattice is harnessed to demonstrate a novel class of gate tunable memristors. (Memristor is a fundamental element in electrical circuits along with resistor, capacitor, and inductor). Conventional memristors, based on metal-insulator-metal structures are limited by the lack of control over filament formation mechanism and switching voltage. The present MoS2 memristors not only show a large switching ratios (103) and but also provide widely tunable characteristics by confining flux of electrons and ions to different parts of the channel defined by shape of the grain boundaries. Furthermore, a third gate terminal in a field-effect geometry offers unprecedented control over switching voltage for novel logic and neural circuit architectures.
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